1. Field of the Invention
The present invention relates to a semiconductor device and more specifically to the structure of array transistors and peripheral transistors (transistors in peripheral circuits) of an embedded or a consumer used dynamic random access memory (DRAM) and a method of manufacturing such a device.
2. Description of the Related Art
FIG. 17 depicts, in a sectional view, the structure of an array transistor which forms a part of a memory cell of a DRAM and a peripheral transistor which forms a part of a peripheral circuit. Each of the transistors is a metal oxide semiconductor field effect transistor (MOSFET, hereinafter referred to simply as a transistor). As shown in FIG. 17, a gate electrode 103 is located on a gate insulating film 102 formed on the surface of a semiconductor substrate 101. A post-oxide film 104 is comprised of a portion 104a located on the sidewall of the gate electrode 103 and a portion 104b located on the semiconductor substrate 101 by the side of the gate electrode 103. A spacer 105 on the post-oxide film 104a covers the sidewalls of the gate electrode 103 and the sidewalls of a silicide film 106 and an insulating film 107 which are located on the gate electrode 103. Source/drain extension layers 108 are formed in portions of the surface of the semiconductor substrate 101 which are located immediately under the portion 104b of the post-oxide film 104.
In order to suppress the short-channel effect of the transistor, it is required to form thin extension layers. The extension layers 108 are formed by means of ion implantation through the post-oxide film 104b; thus, if the post-oxide film 104b is thin, the controllability of ion implantation increases, allowing the extension layers 108 to be formed thin with ease. In particular, with peripheral transistors for which the demand for high performance is increasing, to suppress the short-channel effect, it is advisable that the post-oxide film 104 be thin.
In order to reduce electric fields at the lower corners of the gate electrode 103, it is necessary to make the post-oxide film 104a thick. For instance, it is required that the post-oxide film 104a be thicker than the gate insulating film 102. This is because control of the thickness of the post-oxide film 14a allows the lower corners of the gate electrode 103 to become rounded, thereby reducing the electric field at the lower corners. In view of the fact that contact of a insulating film to the semiconductor substrate 101 prevents tunneling of electrons between bands, it is also required the thickness of the post-oxide film 104a be 10 nm or more at least in the vicinity of the gate electrode 103. With DRAM array transistors in particular, it is desirable that the post-oxide film 104 be thick in order to reduce the electric field at the corners of the gate electrode 103 for the aim of improving data retention characteristics.
In determining the thickness of the post-oxide film 104, the peripheral transistors have to be constructed to conform to the array transistors because the performance of the array transistors is given preference over the performance of the peripheral transistors. That is, the thickness of the post-oxide film 104 is set to thicknesses required of the array transistors. As a consequence, it becomes impossible to improve the performance of the peripheral transistors.